XC3S400-4PQG208I

The Spartan-3 family architecture consists of five fundamental programmable functional elements:
• Configurable Logic Blocks (CLBs) contain RAM-based Look-Up Tables (LUTs) to implement logic and storage
elements that can be used as flip-flops or latches. CLBs can be programmed to perform a wide variety of logical
functions as well as to store data.
• Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. Each IOB
supports bidirectional data flow plus 3-state operation. Twenty-six different signal standards, including eight
high-performance differential standards, are available as shown in Table 2. Double Data-Rate (DDR) registers are
included. The Digitally Controlled Impedance (DCI) feature provides automatic on-chip terminations, simplifying board
designs.
• Block RAM provides data storage in the form of 18-Kbit dual-port blocks.
• Multiplier blocks accept two 18-bit binary numbers as inputs and calculate the product.
• Digital Clock Manager (DCM) blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying,
dividing, and phase shifting clock signals.
These elements are organized as shown in Figure 1. A ring of IOBs surrounds a regular array of CLBs. The XC3S50 has a
single column of block RAM embedded in the array. Those devices ranging from the XC3S200 to the XC3S2000 have two
columns of block RAM. The XC3S4000 and XC3S5000 devices have four RAM columns. Each column is made up of several
18-Kbit RAM blocks; each block is associated with a dedicated multiplier. The DCMs are positioned at the ends of the outer
block RAM columns.
The Spartan-3 family features a rich network of traces and switches that interconnect all five functional elements,
transmitting signals among them. Each functional element has an associated switch matrix that permits multiple connections
to the routing.