• Includes ST state-of-the-art patented
technology
• Core: Arm® 32-bit Cortex®-M7 CPU with
DPFPU, ART Accelerator and L1-cache:
16 Kbytes I/D cache, allowing 0-wait state
execution from embedded flash and external
memories, up to 216 MHz, MPU,
462 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1),
and DSP instructions.
• Memories
– Up to 2 Mbytes of flash, organized into two
banks allowing read-while-write
– SRAM: 512 Kbytes (including 128 Kbytes
of data TCM RAM for critical real-time data)
+ 16 Kbytes of instruction TCM RAM (for
critical real-time routines) + 4 Kbytes of
backup
– Flexible external memory controller with up
to 32-bit data bus: SRAM, PSRAM,
SDRAM/LPSDR SDRAM, NOR/NAND
memories
• Dual mode Quad-SPI
• Graphics
– Chrom-ART Accelerator (DMA2D),
graphical hardware accelerator enabling
enhanced graphical user interface
– Hardware JPEG codec
– LCD-TFT controller supporting up to XGA
resolution
– MIPI® DSI host controller supporting up to
720p 30 Hz resolution
• Clock, reset and supply management
– 1.7 to 3.6 V application supply and I/Os
– POR, PDR, PVD and BOR
– Dedicated USB power
– 4-to-26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC (1%
accuracy)
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
• Low-power
– Sleep, Stop and Standby modes
– VBAT supply for RTC, 32×32 bit backup
registers + 4 Kbytes backup SRAM
• 3×12-bit, 2.4 MSPS ADC: up to 24 channels
• Digital filters for sigma delta modulator
(DFSDM), 8 channels / 4 filters
• 2×12-bit D/A converters
• General-purpose DMA: 16-stream DMA
controller with FIFOs and burst support
• Up to 18 timers: up to thirteen 16-bit (1x lowpower 16-bit timer available in Stop mode) and
two 32-bit timers, each with up to four
IC/OC/PWM or pulse counter and quadrature
(incremental) encoder input. All 15 timers
running up to 216 MHz. 2x watchdogs, SysTick
timer
• Debug mode
– SWD and JTAG interfaces
– Cortex®-M7 Trace Macrocell™
• Up to 168 I/O ports with interrupt capability
– Up to 164 fast I/Os up to 108 MHz
– Up to 166 5 V-tolerant I/Os
• Up to 28 communication interfaces
– Up to four I2C interfaces (SMBus/PMBus)
– Up to four USARTs/4 UARTs (12.5 Mbit/s,
ISO7816 interface, LIN, IrDA, modem
control)
– Up to six SPIs (up to 54 Mbit/s), three with
muxed simplex I2S for audio
– 2 x SAIs (serial audio interface)
– 3 × CANs (2.0B Active) and 2x SDMMCs
– SPDIFRX interface
– HDMI-CEC
– MDIO slave interface
• Advanced connectivity
– USB 2.0 full-speed device/host/OTG
controller with on-chip PHY
– USB 2.0 high-speed/full-speed
device/host/OTG controller with dedicated
DMA, on-chip full-speed PHY and ULPI
– 10/100 Ethernet MAC with dedicated DMA:
supports IEEE 1588v2 hardware, MII/RMII
• 8- to 14-bit camera interface, up to 54 Mbyte/s
• True random number generator
• CRC calculation unit
• RTC: subsecond accuracy, hardware calendar
• 96-bit unique ID