• C Compiler Optimized RISC Architecture
• Operating Speed:
– DC – 32 MHz clock input
– 125 ns minimum instruction cycle
• Interrupt Capability
• 16-Level Deep Hardware Stack
• Timers:
– 8-bit Timer2 with Hardware Limit Timer (HLT)
– 16-bit Timer0/1
• Low-Current Power-on Reset (POR)
• Configurable Power-up Timer (PWRTE)
• Brown-out Reset (BOR)
• Low-Power BOR (LPBOR) Option
• Windowed Watchdog Timer (WWDT):
– Variable prescaler selection
– Variable window size selection
– All sources configurable in hardware or
software
• Programmable Code Protection