KSZ9896CTXI

• Switch Management Capabilities
– 10/100/1000Mbps Ethernet switch basic functions:
frame buffer management, address look-up table,
queue management, MIB counters
– Non-blocking store-and-forward switch fabric assures
fast packet delivery by utilizing 4096 entry forwarding
table with 256kByte frame buffer
– Jumbo packet support up to 9000 bytes
– Port mirroring/monitoring/sniffing:
ingress and/or egress traffic to any port
– MIB counters for fully-compliant statistics gathering
34 counters per port
– Tail tagging mode (one byte added before FCS) support at host port to inform the processor which ingress
port receives the packet and its priority
– Loopback modes for remote failure diagnostics
– Rapid spanning tree protocol (RSTP) support for topology management and ring/linear recovery
– Multiple spanning tree protocol (MSTP) support
• One Ext. MAC Port with GMII/RGMII/MII/RMII
– RGMII v2.0, RMII v1.2 with 50MHz reference clock
input/output option, MII in PHY/MAC mode
• Five Integrated PHY Ports
– 1000BASE-T/100BASE-TX/10BASE-Te IEEE 802.3
– Fast Link-up option significantly reduces link-up time
– Auto-negotiation and Auto-MDI/MDI-X support
– On-chip termination resistors and internal biasing for
differential pairs to reduce power
– LinkMD® cable diagnostic capabilities for determining
cable opens, shorts, and length
• Advanced Switch Capabilities
– IEEE 802.1Q VLAN support for 128 active VLAN
groups and the full range of 4096 VLAN IDs
– IEEE 802.1p/Q tag insertion/removal on per port basis
– VLAN ID on per port or VLAN basis
– IEEE 802.3x full-duplex flow control and half-duplex
back pressure collision control
– IEEE 802.1X access control
(Port-based and MAC address based)
– IGMP v1/v2/v3 snooping for multicast packet filtering
– IPv6 multicast listener discovery (MLD) snooping
– IPv4/IPv6 QoS support, QoS/CoS packet prioritization
– 802.1p QoS packet classification with 4 priority queues
– Programmable rate limiting at ingress/egress ports
– Broadcast storm protection
– Four priority queues with dynamic packet mapping for
IEEE 802.1p, IPv4 DIFFSERV, IPv6 Traffic Class
– MAC filtering function to filter or forward unknown unicast, multicast and VLAN packets
– Self-address filtering for implementing ring topologies
• Comprehensive Configuration Registers Access
– High-speed 4-wire SPI (up to 50MHz), I2C interfaces
provide access to all internal registers
– MII Management (MIIM, MDC/MDIO 2-wire) Interface
provides access to all PHY registers
– In-band management via any of the data ports
– I/O pin strapping facility to set certain register bits from
I/O pins at reset time
– On-the-fly configurable control registers
• Power Management
– Energy detect power-down mode on cable disconnect
– Dynamic clock tree control
– Unused ports can be individually powered down
– Full-chip software power-down
– Wake-on-LAN (WoL) standby power mode with PME
interrupt output for system wake upon triggered events