EP3C5F256C8N

Cyclone® III device family offers a unique combination of high functionality, low
power and low cost. Based on Taiwan Semiconductor Manufacturing Company
(TSMC) low-power (LP) process technology, silicon optimizations and software
features to minimize power consumption, Cyclone III device family provides the ideal
solution for your high-volume, low-power, and cost-sensitive applications. To address
the unique design needs, Cyclone III device family offers the following two variants:
■ Cyclone III: lowest power, high functionality with the lowest cost
■ Cyclone III LS: lowest power FPGAs with security
With densities ranging from 5K to 200K logic elements (LEs) and 0.5 Mbits to 8 Mbits
of memory for less than ¼ watt of static power consumption, Cyclone III device
family makes it easier for you to meet your power budget. Cyclone III LS devices are
the first to implement a suite of security features at the silicon, software, and
intellectual property (IP) level on a low-power and high-functionality FPGA platform.
This suite of security features protects the IP from tampering, reverse engineering and
cloning. In addition, Cyclone III LS devices support design separation which enables
you to introduce redundancy in a single chip to reduce size, weight, and power of
your application.
This chapter contains the following sections:
■ “Cyclone III Device Family Features” on page 1–1
■ “Cyclone III Device Family Architecture” on page 1–6
■ “Reference and Ordering Information” on page 1–12


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    SPECIFICATION

    Cyclone III LS devices offer the following design security features:
    ■ Configuration security using advanced encryption standard (AES) with 256-bit
    volatile key
    ■ Routing architecture optimized for design separation flow with the Quartus® II
    software
    ■ Design separation flow achieves both physical and functional isolation
    between design partitions
    ■ Ability to disable external JTAG port
    ■ Error Detection (ED) Cycle Indicator to core
    ■ Provides a pass or fail indicator at every ED cycle
    ■ Provides visibility over intentional or unintentional change of configuration
    random access memory (CRAM) bits
    ■ Ability to clear contents of the FPGA logic, CRAM, embedded memory, and
    AES key
    ■ Internal oscillator enables system monitor and health check capabilities