• 4 Kbit/16 Kbit SRAM with EEPROM Backup:
– Internally organized as 512 x 8 bits (47X04)
or 2,048 x 8 bits (47X16)
– Automatic Store to EEPROM array upon
power-down (using optional external
capacitor)
– Automatic Recall to SRAM array upon
power-up
– Hardware Store pin for manual Store
operations
– Software commands for initiating Store and
Recall operations
– Store time 8 ms maximum (47X04) or
25 ms maximum (47X16)
• Nonvolatile External Event Detect Flag
• High Reliability:
– Infinite read and write cycles to SRAM
– More than one million store cycles to
EEPROM
– Data retention: >200 years
– ESD protection: >4,000V
• High-Speed I2C Interface:
– Industry standard 100 kHz, 400 kHz and
1 MHz
– Zero cycle delay reads and writes
– Schmitt Trigger inputs for noise suppression
– Cascadable up to four devices
• Write Protection:
– Software write protection from 1/64 of SRAM
array to whole array
• Low-Power CMOS Technology:
– 200 µA active current typical
– 40 µA standby current (maximum)
• Available Temperature Ranges:
– Industrial (I): -40°C to +85°C
– Extended (E): -40°C to +125°C
• Automotive AEC-Q100 Qualified