XCAU10P-2FFVB676I

The UltraScale™ architecture comprises high-performance FPGA, MPSoC, and RFSoC families that address a vast spectrum of
system requirements with a focus on lowering total power consumption through innovative technological advancements.
Spartan™ UltraScale+™ FPGAs: Cost-optimized devices with high I/O to logic ratio and integrated memory controllers for broad based, cost
sensitive applications
Artix™ UltraScale+ FPGAs: Highest serial bandwidth and signal compute density in a cost-optimized device for critical networking applications,
vision and video processing, and secured connectivity.
Kintex™ UltraScale FPGAs: High-performance with a focus on price/performance, using both monolithic and stacked silicon interconnect (SSI)
technology. High DSP and block RAM-to-logic ratios and transceivers, combined with low-cost packaging, enable an optimum blend of capability
and cost.
Kintex UltraScale+ FPGAs: Increased performance and on-chip UltraRAM memory to reduce BOM cost. The ideal mix of high-performance
peripherals and cost-effective system implementation with numerous power options for the optimal balance between the required system
performance and the smallest power envelope.
Virtex™ UltraScale FPGAs: High-capacity, high-performance FPGAs enabled using both monolithic and SSI technology. Virtex UltraScale devices
achieve the highest system capacity, bandwidth, and performance to address key market and application requirements through integration of
various system-level functions.
Virtex UltraScale+ FPGAs: The highest transceiver bandwidth, highest DSP count, and highest on-chip and in-package memory available in the
UltraScale architecture with numerous power options for the optimal balance of the system performance and the smallest power envelope.
Zynq™ UltraScale+ MPSoCs: Combine the Arm® v8-based Cortex®-A53 high-performance energy-efficient 64-bit application processor with
the Arm Cortex-R5F real-time processor and the UltraScale architecture to create programmable MPSoCs. Provide unprecedented power savings,
heterogeneous processing, and programmable acceleration.
Zynq UltraScale+ RFSoCs: Combine RF data converter subsystem and forward error correction with programmable logic and heterogeneous
processing capability. Integrated RF-ADCs, RF-DACs, and soft decision FECs (SD-FEC) provide the key subsystems for multiband, multi-mode
cellular radios and cable infrastructure.


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    SPECIFICATION

    RF Data Converter Subsystem Overview
    Most Zynq UltraScale+ RFSoCs include an RF data converter subsystem, which contains multiple radio
    frequency analog to digital converters (RF-ADCs) and multiple radio frequency digital to analog
    converters (RF-DACs). The high-precision, high-speed, power efficient RF-ADCs and RF-DACs can be
    individually configured for real data or in most cases can be configured in pairs for real and imaginary I/Q
    data. See RF-ADCs and RF-DACs sections.

    Digital Front-End (DFE) Overview
    Zynq UltraScale+ RFSoC DFE devices contain integrated IP cores to perform many of the DFE functions
    required in a 5G radio. With new radio standards rapidly evolving for 5G, combining integrated DFE IP with
    the adaptability of programmable logic provides a low-risk, flexible approach to 5G implementation.

    Soft Decision Forward Error Correction (SD-FEC) Overview
    Some Zynq UltraScale+ RFSoCs include highly flexible soft decision FEC blocks for decoding and encoding
    data as a means to control errors in data transmission over unreliable or noisy communication channels.
    The SD-FEC blocks support low-density parity check (LDPC) decode/encode and Turbo decode for use in
    5G wireless, backhaul, DOCSIS, and LTE applications.

    Processing System Overview
    Zynq UltraScale+ MPSoCs and RFSoCs feature dual and quad core variants of the Arm Cortex-A53 (APU)
    with dual-core Arm Cortex-R5F (RPU) processing system (PS). Some devices also include a dedicated Arm
    Mali™-400 MP2 graphics processing unit (GPU). See Table 2.