D2516EC4BXGGB

D2516EC4BXGGB 4G bits DDR3L SDRAM (256M words x 16 bits)

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    SPECIFICATION

    Key Features
    • Double-data-rate architecture: two data transfers per clock cycle
    • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
    • Bi-directional differential data strobe (DOS and /DQS) is transmitted/received with data for
    capturing data at the receiver
    • DOS is edge-aligned with data for READS; center-aligned with data for WRITES
    • Differential clock inputs (CK and /CK)
    • DLL aligns DQ and DOS transitions with CK transitions
    • Commands entered on each positive CK edge; data and data mask referenced to both
    edges of DQS
    • Data mask (DM) for write data
    • Posted /CAS by programmable additive latency for better command and data bus efficiency
    • On-Die Termination (ODD for better signal quality
    — Synchronous ODT
    — Dynamic CDT
    — Asynchronous ODT
    • Multi Purpose Register (MPR) for pre-defined pattern read out
    • ZQ calibration for DO drive and ODT
    • Programmable Partial Array Self-Refresh (PASR)
    • RESET pin for Power-up sequence and reset function
    • SRT range: Normal/extended
    • Programmable Output driver impedance control