SN74AUP1G08QDCKRQ1

The AUP family is TI’s premier solution to the low-power needs of the industry in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire V_CC range of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).

This single 2-input positive-AND gate performs the Boolean function: Y = A • B or Y = A\ + B\ in positive logic.

NanoStar package technology is a major breakthrough in integrated circuit (IC) packaging concepts, because it uses the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Category: Gates and Inverters

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SPECIFICATION

AEC-Q100 Qualified with the Following Results:
- Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range
- Device HBM ESD Classification Level H2
- Device CDM ESD Classification Level C3B
Available in the Texas Instruments NanoStar Package
Low Static-Power Consumption:
I_CC = 0.9 µA Max
Low Dynamic-Power Consumption:
C_pd = 4.3 pF Typ at 3.3 V
Low Input Capacitance: C_i = 1.5 pF Typ
Low Noise: Overshoot and Undershoot
< 10% of V_CC
I_off Supports Partial-Power-Down Mode Operation
Schmitt-Trigger Action Allows Slow Input Transition and Better
Switching Noise Immunity at the Input (V_hys = 250 mV, Typ at
3.3 V)
Wide Operating V_CC Range of 0.8 V to 3.6 V
Optimized for 3.3-V Operation
3.6-V Input/Output (I/O) Tolerant to Support Mixed-Mode Signal Operation
t_pd = 4.3 ns Max at 3.3 V
Suitable for Point-to-Point Applications
Latch-Up Performance Exceeds 100 mA Per JESD-78, Class II