CY91F526BSCPMC1-GSE2

 32-bit RISC, load/store architecture, pipeline 5-stage
structure
 Maximum operating frequency: 80 MHz (Source oscillation
= 4.0 MHz and 20 multiplied (PLL clock multiplication
system))
 General-purpose register : 32 bits × 16 sets
 16-bit fixed length instructions (basic instruction),
1 instruction per cycle
 Instructions appropriate to embedded applications
 Memory-to-memory transfer instruction
 Bit processing instruction
 Barrel shift order etc.
 High-level language support instructions
 Function entry/exit instructions
 Register content multi-load and store instructions
 Bit search instructions
Logical 1 detection, 0 detection, and change-point detection
 Branch instructions with delay slot
 Overhead reduction during branch process
 Register interlock function
 Easy assembler writing
 The support at the built-in / instruction level of the multiplier
 Signed 32-bit multiplication: 5 cycles
 Signed 16-bit multiplication: 3 cycles
 Interrupt (PC/PS saving)
6 cycles (16 priority levels)
 The Harvard architecture allows simultaneous execution of
program and data access.
 Instruction compatibility with the FR Family
 Built-in memory protection function (MPU)
 Eight protection areas can be specified commonly for
instructions and the data.
 Control access privilege in both privilege mode and
user mode.
 Built-in FPU (floating point arithmetic)
 IEEE754 compliant
 Floating-point register 32-bit × 16 sets